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Login WAH:

   a5101250

chmod 755 -R

*kiem tra dung luong:

   df | grep Backend

   du -csh  Backend

*kiem tra licenses:

   list_licenses

   remove_licenses

   alias: chk_lic

*Check off GUI:

   bjobs -u all | grep -i GUI | egrep 'login01|login09'

*kill jobs:

   bjobs

   ps aux | grep tunglai

   kill -9 No.job

*Tao duong link thu muc:

  ln -sf duong_link_toi_thu_muc_do

*Change tab:

  Ctrl + pageup/pagedown

*Go to first file:

   :rew

*move and back to file:

   GF -> Ctrl O

*Exceed on Demand:

   host: 172.29.143.165

*copy tren sever:

   bs -M 16000 cp -rf  folder_old  folder_new

*fix loi hien thi:

   unix2dos

*check ID cua terminal:

   id

* sleep:

   sleep 5s; go_icc2.tcl

*chay P&R flow:

  go_icc2.tcl  -> open tool icc2

  gf  -> go file

  :bd  -> go back previous file ~ Ctrl+o

  Shift + #  -> highlight keyword -> gf: go file contain highlight word

  :nohl  -> no highlight

  F4: open Task Assistant Dialog

  gg: go head page

  Shift + g: bottom page

  list_licenses

  remove_licenses

* Visual

- Insert

  Ctrl + v  -> chon so dong  -> Shift + i  -> Shift + #  -> Esc Esc

- Delete

  Ctrl+v  -> x

*Copy and paste

  yy -> p

*find word and replace:

  :%s/old_word/new_word/g

*Chen them ky tu vao dau/cuoi dong:

  :%s/^/\/Z \\/g

  :%s/$/\/Z \\/g

*check overlaps:

  check_legality

  report_placement -hard_macro_overlap

*No DCG (optimize netlist)

  Set 2 cho cho DCG (false and NO_DCG)

*Search path VIOLATE:

  /VIO .*-3.4 (gtri -3.4 la gtri te nhat lay tu report timing tai scenario)

*Size cell before run CTS:

  get_attribute [get_selection ] ref_name

  get_lib_cell */CKND2D*BWP7T40P140 (xem cac size cua cell, thong thuong size up > D4

*Tim port clock:

  less mode_DFT.tcl | grep create_clock | grep get_port

  them -v de lay cac dong con lai.

*Tim pin clock:

cat /shsv/Backend5/RCV3M_1/1_design/13_COMMON/work_nga/ICC2/SDC_TOP/ctGEN_TOP_clock_2nd_ver2.dat_Nga | grep -v # | grep create_clock | awk '{print "change_selection -add",$(NF-1),$NF}' | less

*VIOLATE GROUP PATH:

   Sort group path violate: ~/script_design/group_path/mk_pathrep6_skew ten_report_timing_violate

   Sort file lam tu buoc tren: ~/script_design/group_path/hi_GetTNS3_skew ten_file_o_tren > ten_moi

*Size cells:

   foreach_in_collection buf [get_selection] {set name [get_attribute $buf full_name] ;  set ten [get_attribute $buf ref_name]; puts "size_cell $name $ten"} > test

*Xoa partial blockage:

  remove_placement_blockages [get_placement_blockages -hierarchical -filter "blockage_type == partial"]

*Xoa hard blockage:

  change_selection [get_placement_blockages -hierarchical -filter "blockage_type == hard"] -> bam d

*Manual check clock:

     synthesize_clock_trees -propagate_only

     update_timing -full

     report_clock_qor -type latency -nosplit -clocks {OUT_cma_s3d1ck_hier}

     report_clock_qor -type latency -nosplit

     report_clock_qor -type latency -nosplit -show_paths >

*Insert buffer:

   add_buffer [get_pins top/CTS_TRUNK_BUF_s3d1ck_hier_TungLai_u3dg_1/Z] -new_cell_names CTS_TRUNK_BUF_s3d1ck_hier_TungLai_u3dg_2 -new_net_names CTS_TRUNK_NET_s3d1ck_hier_TungLai_u3dg_2 -lib_cell  CKBD4BWP7T40P140 -no_of_cells 1

*get_cells thanh tung hang:

           foreach_in_collection  term [get_cells ] {puts [get_attribute $term full_name]}

*Chuyen ten mot FRAM thanh con CELL    

            change_macro_view -reference G3MHPE_LS -view CEL

*Write Verilog cua toan design tru 1 con SUB bat ki    

        write_verilog -no_physical_only_cells -wire_declaration -diode_ports -macro_definition -force_no_output "uhi19dspcore0" test_verilog_4.v

*Chuyen hard_macro de doc DEF,LEF:        

        uncommit_fp_soft_macros  

*Tool write LEF,DEF.

        bs -M 96000 -os "RHEL6 RHEL5" -source /common/appl/Env/Synopsys/mw_vK-2015.06-SP1 Milkyway

*Giai nen thu muc

                gtar -zvbf foder.tar.gz foder_extract

*Report area:

                report_placement_utilization (don vi la site, 1 sites = 0.1575 um2)

        report_design -physical (don vi la micron nen khong can tinh toan them)        

*Report leakage:

                (phai source cai file defind )

        source /shsv/Backend/EDA_PROJECT/USER/TOP_env3new/DesignV_ICC/tcl_pr/set_vth_ratio_RV40F.tcl

                report_threshold_voltage_group

* Report #ofinstant, #ofMacs, #ofNET,..

                report_design -physical


LAI THANH TUNG 1850----------------------------------------------------------

===================================PnR Flow================================[sửa | sửa mã nguồn]

00. IMPORTANT:

  - insert remove license at the bottom of script & #exit if want to check design in GUI.

  - Save block, save lib after run the command which are important or long time waiting.

01. INPUT:

  - Verilog netlist, reflib FE

  - sign-off (timing, scenario, power leakage, die size)

  - CU

  - Def file

  - Keep list

  - PV

  - SDC file

  - P&R Environment

  - STA take care SDC file and PnR Env

02. FLOORPLAN (INITIAL STEP):

+ Tao Shape (top quy dinh):

    * How to fix sharp to decrease or increase utilization:

       - move macro cell into boundary, turn off standard cell view.

       - report_utilization

       - Create -> Bound -> draw new shape -> cut object shape (X) if want

       - get_attribute [get_selection ] boundary

       - set_attribute [current_design ] boundary {toa do boundary}

       - remove_physical_objects

       - initialize_floorplan -keep_boundary -core_offset {0 0} -flip_first_row true -keep_macro_placement  -keep_block_placement -keep_io_placement  -coincident_boundary true -site_def unit

       - report_utilization

+ Tao Shape dua tren toa do Top giao:

       - set RCARD3 {{-3136.270 -2906.630} {3137.030 2852.170}}

       - set_attribute [current_design ] boundary $RCARD3

       - initialize_floorplan -keep_boundary -core_offset {0} -flip_first_row true -coincident_boundary true -site_def unit


+ Sap xep Hard Macro:

      - Xep theo Group Boundary

      - Khe cach nhau 7um

      - Moi Khoi co chieu ngang co 150:160 um

      - Pin huong vao trung tam, phia co Clock Data Port  (!!!!! chi dung X-axis or Y-axis)

      - Co the sap Hard Macro doi xung de giam duong data path

   * Cach dat hard macro cell doi voi cac cell giong nhau bang cach lay toa do:

      - write_floorplan -objects [get_selection] -output ./lm24.dump

      - source ./lm24.dump/floorplan.tcl

      - vao file floorplan.tcl -> find and replace cell -> source again


+ Tao Port:

     - Tach port clock va data ra rieng?dum

Xem tai (set ICC_IN_IDEAL_DFT_SDC_FILE  "/shsv/Backend/TRAINING/24G/BE1_members/tunglai/data_IMP_V3M_proj/input/sdc/mode_DFT.tcl")

     - Chay script tao port : "make_port.tcl"

        . M3, M5, M7 Horizontal

        . M4, M6 Vertical

     - Khoang cach giua cac Port = khoang cach cua duong Track

     - Tam port trung voi duong Track

     - Chu y chinh sau chieu cao

     - Nho tach Port Clock !!!!

        . change_selection [get_ports {....}]


+ Tao Blockage:

     - Hard :

        . Xung quanh Boundary (1 row & 5 sites)

        . Xung quang Hard Macro :        

              source create_blockage.tcl

              create_blockage macro

              source blockage_macro.tmp

     - Soft : Dung o khe giua cac khoi Hard Macro

     - Partial : Tuy design


+ Fix all items: bam vao icon o khoa

     - Macros: change_selection [get_cells -hierarchical -filter "is_hard_macro == true "]

     - Port

     - Blockage


+ Tao file dump & def:

     -  write_floorplan -include {macros blockages pins} -output tungdeptrai.dump         - set all_macro_cells [get_cells -hierarchical -f "is_hard_macro && !is_physical_only"]

       write_def  -include {rows_tracks blockages cells ports specialnets vias} -objects [add_to_collection $all_macro_cells [get_cells -hierarchical -filter is_physical_only]] tungdeptrai.def


+ Tao bound cho cac khoi atom, tcg, fbj:

     - Muc dich: gom cac cell thuoc cac khoi tcg, fbj lai gan port clock de chay CTS (bat buoc)

     - Ngoai ra 1 vai module dac biet can tao bound de group cac cell lai tai vi tri nao do minh muon (khong bat buoc)

     - Uti cua bounds nen < uti design ~ 10%.

     - Remove bounds truoc khi refine_opt.                

     - Command: get_attribute [get_selection ] boundary

                         create_bound -name ten_bound -boundary { toa do } -type soft {ten_module}

                         get_bounds *


+Check:

     - Site & row  

     - Hard Macro da fix chua

     - Co soft blockage chua

     - Tach Port Clock ra chua (xa so voi Port Data)

     - OVERLAP ko ?

     - Utilization ????


+Run Initial Env:

     - Check 2 files: (the declared variables and the link to other)

        . source -echo ./rm_setup/icc2_flat_setup.tcl

        . source -echo ./rm_setup/icc2_common_setup_CN_ver6_lg35.tcl

     - Check initial env clearly before run auto.

     - Check result in file log and report:

        . PnR route dc va ko short. DRC clean

        . Timing met.

(Dat macro va khu vuc trung tam thoang nhat)

(Tu analyze).

03. PLACEMENT (PRECTS):

+ Do before running placement:

     - Create_placement -effort low

     - Check density, congestion

     - Khu vuc co qua nhieu cell -> tim cac cell do -> make list of keep_out_margin

     - source script insert_IO_BUF.tcl

     - Tao hard macro bao lai khu vuc chua PORT_BUF

     - Trace clock: trace cac pin cua cell toi khi gap FF, float thi dung lai. gap MUX thi trace nguoc lai....

                            co the trace theo full name

                            trace clock de biet dc structure (cau truc) cua khoi atom. giup duong clock di thang (toi uu timing)

                            trong ref_name cua cell ta qtam: CK, size <=D4, SVT (voltage threshole)

     - Tao hard blockage cho clock -> khoa lai bound & cells & ports

     - Tao file dump chua clock, port de source vao env


+ Keep out margin:

     - Dat keep out theo site row (vi du site row la 0.14 thi keep out 0.14, 0.28...)

     - ko can remove cho toi phase cuoi.


+ Set options cho GRC & density:

set_app_options -as_user_default -list { place.congestion_driven_max_util 0.83 }: > uti design ~6-7%

set_app_options -as_user_default -list { place.max_density 0.71 }: < uti design ~2-3%


+ Check env, focus on:

     - DCG

     - DONT_USE

     - PORT_BUF

     - KEEP_LIST

     - KEEP_OUT_MARGIN

     - MCMM


+ Auto xep cell.

+ Thoa man GRC (tu 0.8% tro len thi short nhieu) va Check report timing.

(iDEAL MODE)

+ Neu VIOLATE timing thi tim bugs -> fix

04. CTS:

+ Define SDC clock (vi tri pin, port co clock)

+ Co 2 file DFT va User SDC, lay de dung lam SDC clock.

+ Dung latancy va skew de danh gia tot hay chua.(this is target)

For IP:

+ Trace cac cell khoi atom -> xuat ra file (or xem trong clock structure).

+ Trace khoi jTAG co 4 con MUX, insert buffer vo 1 con co duong net khong qua cell nao het de balance vs cac duong con lai.

+ Cac diem khong can balance: internal FF, float, SRT. Set cho ca 2 pin IN/OUT cua cell.

+ Dont touch net: set dont touch tu port toi het khoi atom. Chi set pin OUT (Z). Luu y: tool van co the insert buffer vao de fix DRC.

For Chip Top:

+ Search pins + ports clocks

+ Choose a clock go though all IP n make a golden trunk tree.

+ Check GRC n Density before make trunk tree.

+ Manual check clock:

       synthesize_clock_trees -propagate_only

       update_timing -full

       report_clock_qor -type latency -nosplit -clocks {OUT_cma_s3d1ck_hier} -show_paths >

05. Post-CTS:

+ Fix clock tren duong Data, dam bao sao cho Data < clk.

06. Route:

+Only route no take care timing:

      route_global: dinh huong duong route (bat via neu can)

      route_auto

      route_detail: dat metal len tracks

+Route optimize:

      route_opt

      route_eco

==> Timing optimize.

==> Clean short, timing met ICC2.(almost met)

================================STA Timing===================================[sửa | sửa mã nguồn]
  • STA:

+ Fix timing

+ Fix transition. => met and PV clean => Tape out.

+ Fix skew.

DN :Dirty netlist.

CN :Clean netlist.

  • ECO flow:

+ Kiem tra xem duong dan den file ECo da dung chua.

+ Kiem tra cac bien ten da phu hop chua: ten cell,

+ Source truoc file ECo roi kiem tra file source_result co Error khong?

  => neu co loi ve toa do thi kiem tra toa do cac con SUB tren TOP voi tung con le co khop nhau khong? Neu khong thi dich toa do con SUB bang command:

                move_mw_cel_origin -to {176.100 1395.450}

  => cac loi khac thi sua de hon.

+ Apply ECO cho tung con SUB thi khi Apply cho TOP phai kiem tra ky FLOW, settup cho dung

+ Check ket qua sau khi Apply ECO xong:

        * Kiem tra Sort bang command: check_route -drc.  

+ Ve viec write Verilog, DEF, LEF, Extract Starcc.      * Write verilog thi co the write bat cu SUB hay TOp hay FULL_Flat.

        * write DEF, LEF              Luc Write Full_FLat thi phai chuyen cac con SUb ve dang CELL de thay duoc ben trong cac con SUB.

          Thuong thi no se default o dang FRAM.                   (Dang VIEW thi co 4 dang: CELL, Abstract, ILM, FRAM)

              + CELL: thay duoc toan bo ben trong SUB

          + Abstract: ben trong SUB se co nhung module khac thi chung ta se thay nhung net, cell tu port den PIN_IN cua module do.

          + ILM:

          + FRAM: chi thay duoc cai bound cua SUB do.

    * Phai uncomix cac con SUB de chuyen cac con SUB do ve Plan Groups.

    * Dung tool moi_Milkyway de write DEF, LEF :  

        bs -M 96000 -os "RHEL6 RHEL5" -source /common/appl/Env/Synopsys/mw_vK-2015.06-SP1 Milkyway

+ Khi chay extract_starcc, de co duoc toa do phai settup lai run_extract  hai bien nay:

         * REDUTION: NO_EXTRA_LOOPS

           NETLIST_NODE_SECTION: YES => no cho ra duoc toa do cua cac cell. (luc truoc la NO se khong cho ra toa do)

+ Khi check_ligaliti thi cac con SUB phai o dang hard_blockage thi moi xem duoc report_overlap (tuc la check design ma khong co uncommit)